This invention relates to programmable logic array integrated circuits, and more particularly to programmable logic array integrated circuits with improved arrangements of the programmable logic elements and improved interconnections between those elements.
Programmable logic arrays are known in which substantial numbers of relatively elementary individual programmable logic elements are provided in a two-dimensional array. The array also includes a grid of intersecting signal conductors for conducting logic signals to, from, and between the programmable logic elements. Such programmable logic arrays are shown, for example, in Carter U.S. Pat. Nos. 4,642,487, 4,706,216, and 4,758,985, and in Freeman U.S. Pat. No. 4,870,302.
As integrated circuit fabrication techniques progress, it becomes possible to put more and more programmable logic elements on a chip. As the number of elements increases, it becomes important to improve the techniques used to interconnect them. For example, it is important to provide enough interconnection pathways between the programmable logic elements so that the capabilities of those elements can be fully utilized and so that complex logic functions (requiring concatenation of programmable logic elements) can be performed, without providing so many such pathways that there is a wasteful excess of this type of resource. Similarly, as the number of programmable elements increases, the complexity of the logic which can be performed also increases. But this in turn tends to increase the complexity of the task of programming the circuit unless additional logical structure is included in the circuit to help correspondingly structure the programming task.
There is always room for further improvement, however, and there are some situations in which the provision of additional or alternative types of interconnections between the logic modules would have benefits sufficient to justify the additional circuit and programming complexity. Such additional interconnection paths may be desirable for making frequently needed kinds of interconnections, for speeding certain kinds of interconnections, for allowing short distance connections to be made without tying up more general purpose and therefore long distance interconnection resources, etc. There is also a continuing demand for logic devices with larger capacity. This produces a need to implement logic functions more efficiently and to make better use of the portion of the device which is devoted to interconnecting individual logic modules.
It is therefore an object of this invention to provide improved programmable logic array integrated circuits.
It is a more particular object of this invention to provide programmable logic array integrated circuits with additional possibilities for interconnections between the logic modules.
It is a further object of this invention to provide improved techniques for organizing and interconnecting the programmable logic elements in programmable logic array integrated circuits.
Finally, another object of this invention is to provide improved programmable logic array integrated circuits.
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic array integrated circuits in which signal conductors are interconnected not by relatively large and complex programmable interconnections, but by relatively small and simple fixed interconnections to multiplexers which can then be programmed to effect the desired interconnections. Instead of having a signal conductor which crosses several other signal conductors programmably connectable to each of those other conductors by programmable elements at or near the intersection, a simple non-programmable transverse connection is made to each of those other conductors, and the transverse connections are applied in parallel to a multiplexer. The multiplexer can then be programmed to select one of its inputs as its output. The output of the multiplexer can be an input to a programmable logic element, an output from the integrated circuit, or a lead which is programmably connectable to one or more of several other conductors in the device.
Another interconnection technique which can be advantageously employed in accordance with the principles of this invention is to group the programmable logic elements into a plurality of mutually exclusive groups, each group having associated with it one or more conductors which can only be used to interconnect the elements in that group. In addition, there are other conductors which can be used to convey signals between the groups. Grouping the programmable logic elements in mutually exclusive (i.e., non-overlapping) groups helps to simplify the task of programming the device by breaking the device down into several discrete parts, each of which is smaller and more easily managed than the whole device. Providing signal conductors which serve only to interconnect the programmable logic elements in each group avoids tying up much longer conductors just to make short interconnections between adjacent programmable logic elements. This helps to reduce the required number of long conductors.
In the above-described arrangement in which the programmable logic elements are grouped and each group is uniquely associated with certain interconnection signal conductors, each programmable logic element may be augmented with a programmable output stage which can be used either to feed the output of that programmable logic element to conductors which go beyond the associated group or to the interconnect conductors of the associated group.
Multiplexers can also be used in combination with programmable signal conductor interconnections to allow certain of the conductors to be laid down more densely, to reduce the size of the interconnection array, and to reduce the capacitive loading on each output conductor of the array. Instead of one output conductor crossing a large number of parallel input conductors with a programmable interconnection at each intersection of the output conductor with the input conductors (which tends to force relatively wide spacing of the input conductors because of the relatively large size of the programmable interconnections), two substantially parallel output conductors feeding a programmably controlled output multiplexer are used. Each of these output conductors has a programmable interconnection only with every other one of the input conductors, and the input conductors which are thus connectable to one of the output conductors are interdigitated with the input conductors which are connectable to the other one of the output conductors. By thus spreading the programmable interconnections somewhat parallel to the longitudinal axes of the input conductors, the input conductors can be placed more closely together, which may save valuable space on the integrated circuit. This technique can also be used and further enhanced to reduce the number of programmable elements required to control the programmable interconnections between the input and output conductors if desired. In particular, a single programmable element can be used to control two interconnections, one of which is on one output conductor, and the other of which is on the other output conductor. The output multiplexer then makes the final selection of the desired output signal. Reducing the number of programmable elements in this way may be especially beneficial when the programmable elements are relatively large (e.g., as compared to the signal conductor interconnection elements they control). Indeed, it may be desirable to use more than two output signal conductors feeding the programmably controlled output multiplexer and to have each programmable element control one interconnection element on each of the more than two output conductors to still further reduce the required number of programmable elements.
Furthermore, other objects of the invention are accomplished in accordance with the principles of this invention by providing programmable logic array integrated circuits which basically employ a highly modular structure of logic elements and logic element interconnection pathways, but which also have one or more of several types of additional interconnection pathways for such purposes as making interconnections locally without tying up resources in the general interconnection structure. For example, such local interconnections may include carry chain interconnections between adjacent or nearby logic modules, or cascade logic connections between such modules in order to allow concatenation of the logic in those modules without recourse to the general interconnection structure. Where, as is preferred, the logic modules are grouped in logic array blocks (xe2x80x9cLABSxe2x80x9d) which are in turn arranged on the integrated circuit in rows and columns, these additional local interconnections may not only be provided between logic modules within a LAB, but also to logic modules in the LABs in another (typically adjacent) row and/or column.
In embodiments employing a network of so-called global horizontal and vertical conductors, interconnections between those conductors are preferably made through tri-state drivers rather than mere passive connections in order to boost signals which may be required to travel relatively long distances through the circuit. Such drivers may alternatively or in addition be used on all logic module output signals which drive relatively long conductors on the circuit.
In addition to the network of global horizontal and vertical conductors typically used for making interconnections between all but relatively closely adjacent logic modules and connections to most of the input and output terminals of the circuit, another auxiliary network of horizontal and vertical conductors (so-called universal fast conductors) may be provided for distributing certain widely used logic signals such as clock and clear signals throughout the circuit. For example, conductors in this universal fast conductor network may be connectable to every logic module in the circuit.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.